This invention relates to low-power-dissipation circuits and, more particularly, to low-power-dissipation circuits fabricated in integrated-circuit (IC) form utilizing complementary metal-oxide-semiconductor (CMOS) technology.
CMOS is generally the currently preferred technology for making IC chips for use in a wide variety of electronic equipment. As the trend to miniaturize such equipment has increased, the use therein of very-large-scale IC chips made in CMOS has become common. The amount of power dissipated in dense arrays of such chips is now often a critical consideration in their design.
Further, the growing importance of portable communication systems has put additional emphasis on the need to design all the component parts of the IC equipment in such systems to exhibit especially low power-dissipation characteristics. In fact, the longevity of the power supplies (batteries) included in these systems is often an important determinant of the usefulness of a system.
Heretofore, it has been proposed to operate metal-oxide-semiconductor (MOS) and CMOS chips in a so-called pulsed-power-supply mode. It was recognized that operation in that mode was a basis for providing chips characterized by low power dissipation. In this connection, see "Hot-Clock nMOS" by C. L. Seitz et al, Proceedings of the 1985 Chapel Hill Conference on VLSI, Computer Science Press, pages 1-17.
But prior known work directed at operating CMOS chips in a pulsed-power-supply mode has consistently specified CMOS circuit configurations that are different and considerably more complicated than the configurations of conventional CMOS circuits operated from a constant-value power supply. In other words, prior known work has not recognized the capability of at least some types of conventional CMOS circuits to operate in the pulsed-power-supply mode.